1. Field of the Invention
The present invention relates to a method for manufacturing a SIMOX wafer using wafer holding means for an oxygen ion implantation apparatus that can improve in-plane thickness uniformity of each of an SOI (Silicon on Insulator) layer and a BOX (Buried Oxide) layer of a SIMOX (Separation by Implanted Oxygen) wafer.
2. Description of the Related Art
A SIMOX technology is a technology for manufacturing a SIMOX wafer by implanting oxygen ions into a silicon substrate at a fixed depth from an ion implantation apparatus, then forming a buried oxide film (which is called a BOX layer), and restoring crystallinity of an SOI layer corresponding to an upper portion of the BOX layer based on a high-temperature heat treatment. At the present day, a method for manufacturing a commercially available SIMOX wafer is called an MLD (Modified Low Dose) method, and oxygen ion implantation is performed on two stages according to this method (see, e.g., Patent Document 1). The first oxygen ion implantation is carried out while heating a silicon wafer, and the subsequent second oxygen ion implantation is performed while reducing a temperature of the silicon wafer to a room temperature or so. In the first oxygen ion implantation, when the oxygen ion implantation is effected while heating the silicon wafer, a high-concentration layer of oxygen is formed while maintaining a silicon wafer surface in a single-crystal state. The second oxygen ion implantation is effected while reducing a temperature, thereby forming an amorphous layer. Then, a high-temperature heat treatment is carried out in a mixed gas containing oxygen and argon, and hence a BOX layer and an SOI layer are formed, thereby forming an SOI configuration.
According to this method, oxygen precipitation is effectively promoted based on an ITOX (Internal Oxidation) technology that forms the amorphous layer on the silicon wafer and further forms a defective layer thereon by the second oxygen ion implantation at a room temperature, and then changes an oxygen concentration on two stages to carry out the high-temperature heat treatment, thus providing an excellent quality of the BOX layer. That is, in the high-temperature heat treatment step, the defective layer functions to promote diffusion of oxygen. As a result of examining oxygen ion implantation conditions in further studies/developments, it has been revealed that surface roughness of the wafer and interface roughness of the SOI layer and the BOX layer can be improved by a method for heating the silicon wafer in the first oxygen ion implantation and performing preheating at a temperature lower than a wafer heating temperature at the time of the first oxygen ion implantation in the second ion implantation (see, e.g., Patent Document 2).
At present, an oxygen ion implantation apparatus used for SIMOX wafer manufacture utilizes wafer holding means whose back surface is prevented from coming into contact with a wafer or very partially brought into contact with the same and which fixes an outer peripheral portion of the wafer by holding pins and the like. When the wafer holding means adopting such a conformation is used, heating is performed by a heater provided on a back surface of the wafer as means for heating the wafer, whereby a temperature of the wafer is increased to effect ion implantation. However, according to the wafer holding means that is not brought into contact with the wafer back surface or is quite partially brought into contact with the same to hold the outer peripheral portion of the wafer, heat generated during heating or ion implantation runs from the holding pins, and a temperature of the wafer near the pins is reduced to be lower than temperatures of other portions due to a heat radiation effect of the pins, whereby a problem that a temperature of the wafer becomes uneven occurs. The unevenness of the temperature degrades film thickness distributions of the finally formed SOI layer and BOX layer. To solve this problem, there are attempts to suppress heat dissipation by using a material having low thermal conductivity for the holding pins. As one of such attempts, an invention that uses a thermosetting resin having low head conductivity as a material of the holding pins is disclosed (see, e.g., Patent Document 3). Further, as another improving method, an invention that incorporates a heater in a wafer contact portion to perform partial heating is disclosed (see, e.g., Patent Document 4).
On the other hand, there is disclosed an ion implantation apparatus that air-tightly closes an opening portion of an apparatus main body with a cover body having a mount for a processing target provided thereon, discharges air in the thus obtained airtight atmosphere to form a vacuum, then performs ion implantation processing with respect to the processing target while flowing a refrigerant through a flow path formed in the mount to cool the processing target on the mount, restores the airtight atmosphere to barometric atmosphere and opens the cover body after ion implantation processing, and replaces the processing target on the mount (see, e.g., Patent Document 5). In this ion implantation apparatus, heat medium supplying means for supplying a heat medium to the flow path is provided. Furthermore, this apparatus is configured to perform switching control over a fluid in the flow path in such a manner that a control unit supplies the heat medium to the flow path from the heat medium supplying means in place of the refrigerant while the cover body is still opened. In the thus configured ion implantation apparatus, since the heat medium is supplied from the heat medium supplying means to the flow path to heat the mount while the cover body is opened, adsorption of moisture onto the mount surface is reduced. As a result, it is possible to decrease a time required for discharging air to form a vacuum after the cover body is closed.
Patent Document 1
Specification of U.S. Pat. No. 5,930,643 (claims 1, 6, 7, 14, and 15)
Patent Document 2
Japanese Patent Application Laid-open No. 2007-5563 (KOKAI) (claims 1 and 2, paragraphs [0011] to [0017], FIGS. 2 and 3)
Patent Document 3
PCT National Publication No. 2007-511899 (claims 1, 17, 19, and 21, paragraphs [0013] to [0015] and [0045] to [0049])
Patent Document 4
Japanese Patent Application Laid-open No. 2007-59262 (claims 1 to 3, paragraphs [0017] to [0022])
Patent Document 5
Japanese Patent Application Laid-open No. 1997-27462 (claim 2, paragraph [0008])
As described above, the oxygen ion implanting steps in manufacture of a SIMOX wafer have a problem that heat generated during the oxygen ion implantation runs from the holding pins of the wafer holding means, a temperature of the wafer near the pins is reduced as compared with other portions to provide non-uniform in-plane temperature distribution of the wafer, and film thickness distributions of the finally formed SOI layer and BOX layer are thereby degraded. In particular, this problem is prominent in the second oxygen ion implanting step that is carried out while reducing the temperature in the MLD method. Patent Documents 3 and 4 disclose countermeasures against this problem.
However, according to the invention disclosed in Patent Document 3, since a coefficient of thermal conductivity is not zero even if a thermosetting resin is used, heat dissipation from the wafer holding portion cannot be completed blocked, and fundamental means for solving the problem is not provided as the case stands. The invention disclosed in Patent Document 4 has a problem that using a partial heater to accurately heat the contact portion alone is difficult. Moreover, the invention disclosed in Patent Document 5 has a problem that an in-plane temperature of the wafer becomes uneven since the mount that holds the processing target is not heated but cooled at the time of ion implantation.